Some integrated circuits contain metal replacement gate transistors, formed by removing sacrificial gates. Sacrificial gates which are removed after forming a dielectric fill layer require the dielectric material to be removed over the sacrificial gates. Removing the dielectric material to expose the sacrificial gates with chemical mechanical polish (CMP) processes risks non-uniform polishing across the integrated circuit and resultant non-uniformity in heights of the replacement metal gates, and/or bridging metal between adjacent gates. Removing the dielectric material with etch processes risks non-uniform exposure of the sacrificial gates and undesirable topography in the dielectric material.